1. Field of the Invention
The present invention relates to a semiconductor device, especially a semiconductor device having a gate oxide film, which is provided adjacent to a region isolating element and has a suitable structure, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
An element-isolating region, which electrically isolates elements in a semiconductor device, has been formed. The local Oxidation of Silicon (LOCOS) method has been frequently used to provided the element-isolating region. In the LOCOS method, however, a bird-beak is produced in the element-isolating region by the thermal oxidation in the LOCOS method. Accordingly, it was difficult to make small the element-isolating region, causing a barrier in the high integration of the semiconductor device.
In recent years, the Shallow Trench Isolation (STI) method has been proposed, which employs a trench structure to provide the element-isolating region.
The element-isolating region is provided, for example, as described below by the STI method.
A pad oxide film and a mask nitride film are formed on the surface of a silicon substrate (hereinafter “Si substrate”) in this order. An area corresponding to the element-isolating region is exposed by patterning using a photolithography etching. A trench is formed by the Reactive Ion Etching (RIE) method using a patterned nitride film as an etching mask. Afterward, an oxide film is formed in the bottom and side walls of the trench (generally called “side-wall oxide film”) by the thermal oxidation method to reduce the influences caused by a damage, such as a defective produced in side the trench by the RIE method. A silicon oxide film (CVD film) is buried in the Si substrate with the trench by Chemical Vapor Deposition (CVD) method. The surface of the Si substrate is made flat by the Chemical Mechanical Polish (CMP) method. Then, the mask nitride film and the pad oxide film are removed to provide the element-isolating region. The element-isolating region (hereinafter sometimes “STI oxide film”) is composed of the side-wall oxide film and the CVD oxide film.
Afterward, when a gate oxide film is formed in an active region, an oxide film is formed by the thermal oxidation and removed so as to remove the damage caused by the etching and improve the quality of the gate oxide. The gate oxide film is formed in the active region, for example, by the thermal oxidation and then, a gate electrode is formed.
In such a conventional STI method, a hollow is produced around the side wall of the STI oxide film by the etching. If the gate oxide film is formed with the presence of the hollow, the thickness of the gate oxide film becomes small partly or the shape of the gate oxide film becomes pointed (sometimes called “pointed portion”). If the gate electrode is formed in the active and element-isolating regions with such a shape of the gate oxide film, malfunction, such as reduction of gate breakdown voltage and generation of leakage current, may easily occur.
Japanese Patent Application Kokai Number 2000-306989 proposes that a protective film is formed along the side wall of the element-isolating region and the pad oxide film is subject to etching to prevent the formation of the hollow produced in the element-isolating region. When the protective film is formed in the side wall of the element-isolating region with the hollow, the gate oxide film is made flat and the channel length of a transistor is not made small.
When making flat the Si substrate by CMP in the conventional method of forming the STI oxide film, since the mask nitride film acts as a stopper, the surface of the STI oxide film is formed at a position higher than the surface of the Si substrate. It is ideal that the surface of a wafer is uniformly made flat by this CPM process. Actually, however, the polishing speed is different according to difference in the density of the element pattern and the position of the element pattern in the surface of the wafer. Consequently, it is possible that the height of the surface of the STI oxide film is partly equal to or lower than the surface of the Si substrate.
When the height of the surface of the STI oxide film is equal to or lower than that of the surface of the Si substrate, the wafer easily receives the influences of the hollow caused by etching.
FIG. 4(A) shows the side-wall oxide film formed by the conventional forming method of the STI oxide film. A pad oxide film 202 and a mask nitride film 204 are formed on a Si substrate 200 in this order and then, a trench 206 is formed. The bottom and side wall of the trench 206 are oxidized by the thermal oxidation method to provide a side-wall oxide film 208. At this point, an edge region 218 is formed, which is a boarder region between the side-wall oxide film 208 and the Si substrate 200 and surrounded by a circle of a dotted line. The edge region is prone to be oxidized by the influence of the pad oxide film 202 during the thermal oxidation process of the trench 206.
FIG. 4(B) shows the element-isolating region and its vicinity after a gate electrode 216 is formed. A gate oxide film 214 is formed on an active region 220 in the Si substrate 200. The element-isolating region or the STI oxide film 212 is composed of the side-wall oxide film 208 and a CVD oxide film 210. The gate electrode 216 is formed in the active region 220 and part of the STI oxide film 212.
The surface of the STI oxide film 212 is polished by CMP and the height thereof is made substantially equal to the surface of the Si substrate 200.
When the height of the surface of the STI oxide film is equal to or lower than that of the surface of Si substrate, the wafer is prone to have the influences of the hollow caused by etching. Also, as shown in FIG. 4(A), since the side-wall oxidation of the edge region 218 is deep, when the gate oxide film is formed after etching the edge region, a pointed portion 224 is frequently produced at the gate oxide film 214. In addition, the thickness of the gate oxide film 214 in the edge region frequently becomes small.
The gate oxide film 214 adjoins to a diffusion region (drain and source regions) in a direction of the channel length (direction perpendicular to the sheet of the drawings). As shown in FIG. 4(B), when the gate electrode is formed in the active region and part of the element-isolating region, that is, when the gate electrode 216 is formed in a direction perpendicular to the channel length direction, the gate oxide film 214 adjoins to the STI oxide film 212. Since electrical charges are easily collected to the edge region 218 of the gate oxide film 214, if the pointed portion 224 is present or the gate oxide film 214 has a thin film at the edge region 218, malfunction, such as reduction of the gate breakdown voltage and generation of the leak current, may occur.
Accordingly, there has been required a semiconductor device and a method of manufacturing the same, which has (1) an element-isolating region or an STI oxide film of which surface is formed at a position higher than the surface of a Si substrate in whole area of a wafer and (2) a gate oxide film having an increased breakdown voltage.
Applicant of this invention came to the conclusion that it is possible to form such an STI oxide film and gate oxide film by etching the Si substrate after forming the STI oxide film by CMP.